An integrated circuit testing probe typically has a multiplicity of test points with ends or tips in a test point plane. Probes having from sixteen to four hundred of these test points are common. During testing of an integrated circuit wafer or chip, these test points are moved into contact with test locations in the plane of a surface of the integrated circuit wafer. Difficulties are encountered in making contact between each of these test points and the test locations on the wafer surface unless the test point plane and the wafer surface are parallel to one another.
Therefore, a need exists for a method and apparatus for effectively establishing parallelism between a test point plane of a probe and the surface of an integrated circuit wafer which is to be probed.